Self-aligned thin film transistor and fabrication method thereof

ABSTRACT

Disclosed are a self-aligned thin film transistor capable of simultaneously improving an operation speed and stability and minimizing a size thereof by forming source and drain electrodes so as to be self-aligned, and a fabrication method thereof. The method of fabricating a thin film transistor according to an exemplary embodiment of the present disclosure includes: forming an active layer, a gate insulator, and a gate layer on a substrate; forming a photoresist layer pattern for defining a shape of a gate electrode on the gate layer; etching the gate layer, the gate insulator, and the active layer by using the photoresist layer pattern; depositing a source and drain layer on the etched substrate by a deposition method having directionality; and forming a gate electrode and self-aligned source electrode and drain electrode by removing the photoresist layer pattern.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a divisional application of co-pending U.S. application Ser. No.14/031,100, filed Sep. 19, 2013. Furthermore, this application is basedon and claims priority to Korean Patent Application No. 10-2012-0133471,filed on Nov. 23, 2012, with the Korean Intellectual Property Office.The disclosures of these prior applications are incorporated herein byreference.

TECHNICAL FIELD

The present disclosure relates to a self-aligned thin film transistor,and a fabrication method thereof, and more particularly, to a technologyof forming source and drain electrodes of a thin film transistor with aseparate electrode material, not by doping for an oxide semiconductor.

BACKGROUND

A thin film transistor employing an oxide semiconductor as an activelayer may be processed at a low temperature and with low costs, and alsoobtain a high mobility characteristic, thereby attracting attentions asa backplane device of an active drive-type display. Recently,technologies of forming source and drain electrodes so as to beself-aligned by using a gate electrode as a mask in manufacturing anoxide semiconductor thin film transistor have been suggested.

FIG. 1 is a configuration diagram of a thin film transistor in therelated art.

In the related arts, source and drain electrodes are formed by dopinghydrogen in source and drain regions or performing a plasma treatment onthe source and drain regions. However, in a case where theaforementioned methods are performed, as a subsequent process, such as aheat treatment, is performed, a doping effect gradually deteriorates, sothat there is a possibility in that an operation characteristic of atransistor will deteriorate. In a case where an element, other thanhydrogen, is doped, an activation temperature of a dopant is high, sothat a problem may occur in that it is difficult to apply the method toa substrate, such as glass or plastic, having a poor heat resistancecharacteristic.

In order to implement a high resolution display, a region occupied by athin film transistor within one pixel may be decreased by minimizing asize of the thin film transistor, and according to the related art, itis necessary to form the source and drain electrodes through the dopingand then connect a separate wiring electrode to source and drainelectrodes of the thin film transistor for an electronic circuitconfiguration. In this case, as illustrated in FIG. 1, in order to forman electrode connected to the source and drain regions, a marginnecessary for mask alignment and a margin for a length and a width of acontact hole are generated, and as a result, there is a problem in thatwidths of the source and drain regions are increased.

SUMMARY

The present disclosure has been made in an effort to provide a thin filmtransistor capable of simultaneously improving an operation speed andstability and minimizing a size thereof by forming source and drainelectrodes so as to be self-aligned by using a separate electrodematerial, not by doping, and a fabrication method thereof.

An exemplary embodiment of the present disclosure provides a method offabricating a self-aligned thin film transistor, including: forming anactive layer, a gate insulator, and a gate layer on a substrate; forminga photoresist layer pattern for defining a shape of a gate electrode onthe gate layer; etching the gate layer, the gate insulator, and theactive layer by using the photoresist layer pattern; depositing a sourceand drain layer on the etched substrate by a deposition method havingdirectionality; and forming a gate electrode and self-aligned sourceelectrode and drain electrode by removing the photoresist layer pattern.

In the etching, the gate layer may be etched so that a width of the gateelectrode is smaller than a shape of the photoresist layer pattern. Theactive layer may be etched by adjusting an etching depth so that a partof a bottom portion of the active layer is left on the substrate.

The method may further include, when parts of the formed sourceelectrode and drain electrode are formed on side walls of the etchedactive layer and gate insulator to be in contact with the gateelectrode, oxidizing the parts of the source electrode and the drainelectrode through a heat or plasma treatment.

Another exemplary embodiment of the present disclosure provides a methodof fabricating a thin film transistor, including: forming an activelayer, a gate insulator, and a gate layer on a substrate; forming afirst photoresist layer pattern for defining a shape of a gate electrodeon the gate layer; etching the gate layer, the gate insulator, and theactive layer by using the first photoresist layer pattern; depositing asource and drain layer on the etched substrate by a deposition methodhaving directionality; forming a second photoresist layer pattern fordefining a shape of a source electrode and a drain electrode on thesource and drain layer; etching the source and drain layer by using thesecond photoresist layer pattern; and forming a gate electrode andself-aligned source electrode and drain electrode by removing the firstand second photoresist layer patterns.

Yet another exemplary embodiment of the present disclosure provides aself-aligned thin film transistor, including: a substrate; an activelayer formed on the substrate; a source electrode and a drain electrodeformed on the substrate and self-aligned in both side surfaces of theactive layer; a gate insulator formed on the active layer; and a gateelectrode formed on the gate insulator.

According to the exemplary embodiments of the present disclosure, it ispossible to provide a thin film transistor capable of minimizingparastic capacitor generation between a gate electrode and source anddrain electrodes to achieve a high-speed operation, guaranteeingoperation stability, and having a smaller size.

According to the exemplary embodiments of the present disclosure, a gateinsulator and a gate electrode are deposited right after deposition ofan oxide semiconductor layer (active layer), so that the insulator andthe electrode may serve as a passivation layer, thereby preventingdamage that may occur during various processes. Accordingly, it ispossible to improve performance and reliability of a device, and anoperation characteristic of the thin film transistor does notdeteriorate even though a subsequent process including heat treatment isperformed.

A high-temperature process for activating a dopant is not required whenthe thin film transistor is fabricated, so that the present disclosuremay be applied to a substrate, such as glass or plastic.

The foregoing summary is illustrative only and is not intended to be inany way limiting. In addition to the illustrative aspects, embodiments,and features described above, further aspects, embodiments, and featureswill become apparent by reference to the drawings and the followingdetailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a configuration diagram of a thin film transistor according tothe related art.

FIGS. 2A to 2F are views for describing a method of fabricating a thinfilm transistor according to an exemplary embodiment of the presentdisclosure.

FIGS. 3A to 3E are views for describing a process of fabricating a thinfilm transistor according to another exemplary embodiment of the presentdisclosure.

FIGS. 4 to 8 are views for describing various methods of forming gate,source, and drain electrodes.

FIG. 9 is a view illustrating an operation characteristic of a thin filmtransistor actually fabricated according to the exemplary embodiments ofthe present disclosure.

DETAILED DESCRIPTION

In the following detailed description, reference is made to theaccompanying drawing, which form a part hereof. The illustrativeembodiments described in the detailed description, and drawings are notmeant to be limiting. Other embodiments may be utilized, and otherchanges may be made, without departing from the scope of the invention.

FIGS. 2A to 2F are views for describing a method of fabricating a thinfilm transistor according to an exemplary embodiment of the presentdisclosure.

Referring to FIGS. 2A to 2F, a method of fabricating a thin filmtransistor according to an exemplary embodiment of the presentdisclosure includes sequentially forming an active layer 203, a gateinsulator 205, and a gate layer 207 on a substrate 201, forming aphotoresist layer pattern 209 for defining a shape of a gate electrodeon the gate layer 207, sequentially etching the gate layer 207, the gateinsulator 205, and the active layer 203 by using the photoresist layerpattern 209, depositing a source and drain layer 211 on the etchedsubstrate 201 by a deposition method having directionality, and forminga gate electrode 207 a, and self-aligned source electrode 211 a anddrain electrode 211 b by removing the photoresist layer pattern 209.

First, as illustrated in FIG. 2A, the active layer 203, the gateinsulator 205, and the gate layer 207 are sequentially deposited on thesubstrate 201, such as glass or plastic.

The active layer 203 may be formed of an oxide semiconductor, and theoxide semiconductor may be formed of zinc oxide (ZnO), indium oxide(InO), indium gallium zinc oxide (In—Ga—Zn—O), and zinc tin oxide(Zn—Sn—O), or oxide containing at least two elements among zinc (Zn),indium (In), gallium (Ga), tin (Sn), and aluminum (Al). Otherwise, theoxide semiconductor may be formed by doping various elements, forexample, Zr, Hf, B, and Ni, on the oxide, or adding the various elementsto the oxide in a form of a compound.

The gate insulator 205 may be formed of oxide, such as Al₂O₃, HfO₂,ZrO₂, TiO₂, SiO₂, Ga₂O₃, Gd₂O₃, V₂O₃, Cr₂O₃, MnO, Li₂O, MgO, CaO, Y₂O₃,and Ta₂O₅, or nitride, such as SiON, SiN_(x), and HfN_(x).

The gate layer may be formed of a material containing at least one ofaluminum (Al), an aluminum alloy (Al alloy), tungsten (W), copper (Cu),nickel (Ni), chrome (Cr), molybdenum (Mo), titanium (Ti), platinum (Pt),tantalum (Ta), indium tin oxide (ITO), and indium zinc oxide (IZO).

Next, as illustrated in FIGS. 2B and 2C, the photoresist layer pattern209 having the shape of the gate electrode is formed on the gate layer207, and then the gate layer 207, the gate insulator 205, and the activelayer 203 are sequentially etched by using the photoresist layer pattern209 as an etching mask. Through this, the gate electrode 207 a is formedon the etched active layer 203 a and gate insulator 205 a.

Next, as illustrated in FIGS. 2D and 2E, the source and drain layer 211is deposited by the deposition method having directionality and then thephotoresist layer pattern 209 is removed. Through this, the source anddrain layer present on the gate electrode 207 a is removed, so that theself-aligned source electrode 211 a and drain electrode 211 b are formedon the gate electrode 207 a.

Subsequently, as illustrated in FIG. 2F, electrodes 215, 215 a, and 215b, and a passivation layer 213 for transceiving data may be furtherformed while being in contact with the gate electrode 207 a, the sourceelectrode 211 a, and the drain electrode 211 b, respectively.

FIGS. 3A and 3E are views for describing a method of fabricating a thinfilm transistor according to another exemplary embodiment of the presentdisclosure.

First, as illustrated in FIGS. 3A and 3B, an active layer 303, a gateinsulator 305, and a gate layer 307 are sequentially deposited on asubstrate 301, and then a photoresist layer pattern 309 is formed. Inthis case, a slope of a side wall of the photoresist layer pattern 309may be negative.

Next, as illustrated in FIGS. 3C and 3D, the gate layer 307, the gateinsulator 305, and the active layer 303 are sequentially etched by usingthe photoresist layer pattern 309 as an etching mask, and a source anddrain layer 311 is deposited thereon by a deposition method havingdirectionality. In this case, as illustrated in FIG. 3C, the activelayer 303 is not totally etched, but may be partially left, and throughthis, a better contact between a source electrode 311 a and a drainelectrode 311 b, and an active layer 303 a to be subsequently formed maybe achieved. A side wall of the etched active layer 303 a may have apositive slope, so that it is possible to prevent void from beinggenerated between the active layers 303 a when the source and drainlayer 311 is deposited.

Next, as illustrated in FIG. 3E, the self-aligned source electrode 311 aand drain electrode 311 b are formed on a gate electrode 307 a byremoving the photoresist layer pattern 309.

In the meantime, in the exemplary embodiment of FIGS. 3A to 3E, theremay occur a case where a source and drain layer 411 completely coversthe etching shape of the gate electrode 307 a because directionality ofthe deposition method is weak when the source and drain layer 411 isformed as illustrated in FIG. 4, so that in this case, it is not easy toremove the photoresist layer pattern 309. In order to prevent theaforementioned case, a gate electrode 507 may be formed in a form havinga narrower width than a shape of the photoresist layer pattern 309 byetching the gate layer 307 more deeply as illustrated in FIGS. 5A and5B. In this case, a shading region is generated under the photoresistlayer pattern 309, so that a source and drain layer 511 is not depositedon a side wall of the gate electrode 507, and through this, a shortphenomenon due to a contact between the gate electrode 507 and thesource and drain layer 511 may be prevented.

In a case where the gate electrode 507 is in contact with a source anddrain layer 611 as illustrated in FIG. 6 even though the methodillustrated in FIGS. 5A and 5B is used, a insulator may be formed byoxidizing a part of the source and drain layer 611 through a heat orplasma treatment as illustrated in FIG. 7. In this case, a part of thedeposited source and drain layer 611 deposited on the side wall portionsof the gate electrode 507 and a gate insulator 305 a to meet the gateelectrode 507 may be oxidized to be a nonconductor, and parts of asource electrode 311 a and a drain electrode 311 b meeting the activelayer 303 a may not be oxidized.

In the meantime, as illustrated in FIG. 8, a photoresist layer pattern801 may be additionally formed in order to define a shape of the sourceelectrode 211 a and the drain electrode 211 b in the exemplaryembodiment of FIGS. 2A to 2F. In this case, source and drain regions aredefined by forming the photoresist layer pattern 801 having the shape ofthe source and drain electrodes 211 a and 211 b before removing thephotoresist layer pattern 209 having the shape of the gate electrode 207a, and the two photoresist layer patterns 209 and 801 may be removed atthe same time. In another case, source and drain electrodes 211 a and211 b are defined by forming the photoresist layer pattern 801 afterhaving removed the photoresist layer pattern 209.

FIG. 9 is a graph illustrating drain current I_(d) according to a gatevoltage V_(g) of the thin film transistor actually fabricated accordingto the exemplary embodiments of the present disclosure, and it can beseen that a general switching operation of the thin film transistor issmoothly performed.

From the foregoing, it will be appreciated that various embodiments ofthe present disclosure have been described herein for purposes ofillustration, and that various modifications may be made withoutdeparting from the scope and spirit of the present disclosure.Accordingly, the various embodiments disclosed herein are not intendedto be limiting, with the true scope and spirit being indicated by thefollowing claims.

What is claimed is:
 1. A self-aligned thin film transistor, comprising:a substrate; an active layer formed on the substrate; a source electrodeand a drain electrode formed on the substrate and self-aligned in bothside surfaces of the active layer; a gate insulator formed on the activelayer; and a gate electrode formed on the gate insulator.
 2. Theself-aligned thin film transistor of claim 1, wherein the active layeris formed of oxide containing at least one element of zinc (Zn), indium(In), gallium (Ga), tin (Sn), and aluminum (Al).
 3. The self-alignedthin film transistor of claim 1, wherein the gate layer is formed of amaterial containing at least one of aluminum (Al), an aluminum alloy (Alalloy), tungsten (W), copper (Cu), nickel (Ni), chrome (Cr), molybdenum(Mo), titanium (Ti), platinum (Pt), tantalum (Ta), indium tin oxide(ITO), and indium zinc oxide (IZO).